1. Field
The present invention relates to biasing techniques in integrated circuit (IC) chips. In particular, the invention relates to testing the error margin as a function of biasing in a system that supports proximity communication.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including hundreds of millions of transistors, into a single semiconductor chip. Integrating such large-scale systems onto a single semiconductor chip increases the speed at which such systems can operate because signals between system components do not have to cross chip boundaries, and are not subject to lengthy chip-to-chip propagation delays. Moreover, integrating large-scale systems onto a single semiconductor chip significantly reduces production costs because fewer semiconductor chips are required to perform a given computational task.
However, these semiconductor chips still need to communicate with each other, and unfortunately these advances in semiconductor technology have not been matched by corresponding advances in inter-chip communication technology. Semiconductor chips are typically integrated onto a printed circuit board that contains multiple layers of signal lines for inter-chip communication. However, signal lines are typically 100 to 1000 times denser on a semiconductor chip than on a printed circuit board. Consequently, only a tiny fraction of the signal lines on a semiconductor chip can be routed across the printed circuit board to other chips. This problem is creating a bottleneck that is expected to worsen as semiconductor integration densities continue to increase.
One solution to the above problem is to replace the direct conductive coupling with direct chip-to-chip capacitive coupling, referred to as “proximity communication” (PxC). Proximity communication is an I/O technology that allows two chips in face-to-face alignment to communicate without wires as has been explained by Drost et al. in “Proximity Communication,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, September 2004, pp. 1529-1535. In the most widely used implementation, corresponding arrays of electrode plates or pads are formed in the opposing surfaces of the two chips, which are then fixed together with a dielectric layer in between to form a large number of capacitively coupled communication links between the chips. One embodiment of a capacitively coupled communication system is illustrated in the circuit diagram of FIG. 1. A first integrated circuit chip, here called a transmit chip 10, includes a transmitter 12 as well as other integrated circuitry typical of a modern IC. A second integrated circuit chip, here called a receive chip 14, includes a receiver 16 as well as other integrated circuitry which needs to be coupled to the circuitry of the transmit chip 10. In this embodiment, the transmitter 12 and receiver 16 are differential, each having either two outputs or two inputs for usually complementary versions of the same signals. Conductive transmit pads 18A, 18B are formed in the surface of the transmit chip 10 and are connected to the differential outputs of the transmitter 12 receiving an input signal VIN across its differential inputs. Similarly, conductive receive pads 20A, 20B are formed in the surface of the receive chip 14 in positions to be aligned with the transmit pads 18A, 18B of the transmit chip 10. The receive pads 20A, 20B are connected to the differential inputs of the receiver 16 outputting an output signal VOUT, which should correspond to VIN.
Typically the pads 18A, 18B, 20A, 20B are covered with thin dielectric layers as part of their formation process. To achieve a proximity communication system, the transmit and receive chips 10, 14 are permanently or semi-permanently juxtaposed with the transmit pads 18A, 18B aligned with respective ones of the receive pads 20A, 20B with a dielectric layer between them, thereby forming two capacitive coupling circuits 22A, 22B between the two chips 10, 14 for the differential signal to be coupled between them.
However, the capacitive coupling circuits 22A, 22B provide DC isolation between the two chips 10, 14 and the high input impedance of the differential amplifier of the receiver 16 provides very little conductive discharge to ground. As a result, receiver nodes 26A, 26B receiving the capacitively coupled signals are floating relative to the transmit chip 10 and are not DC tied to the outputs of the transmitter 12. As a result, the receiver nodes 26A, 26B may suffer DC wander due to leakage and the input offset voltage of the receiver 16 subtract from any signal coupled to it across the capacitive coupling circuits 22A, 22B.
The signals coupled across a DC-isolated capacitively coupled channel can be very small, on the order of tens of millivolts. The input offset voltages in the differential amplifier associated with the receiver 16 used to receive the signals can approach the same order of signal level. Mitigating the effect of the receiver offset advantageously increases their sensitivity and performance. Some prior offset cancellation schemes add capacitance to sensitive nodes in the proximity channel to bias the nodes 26A, 26B toward desired voltage levels. Some prior art schemes dynamically refresh nodes 26A, 26B such that the nodes 26A, 26B are intermittently charged to desired voltage levels during a quiescent period of data transmission.